The integration density of semiconductor integrated circuit devices has been improved with the microfabrication of transistor elements and these devices are now capable of implementing multiple functions with a single semiconductor chip. Further, the microfabrication of transistor elements has been accompanied by progress in increasing the storage capacity of semiconductor memories, regardless of the type thereof, such as a DRAM (Dynamic Random-Access Memory) or SRAM (Static Random-Access Memory).
However, functions and memory capacity that exceed even the increases in multiple functions and memory capacity obtained by microfabrication of transistor elements are sought in recent semiconductor integrated circuit devices, and the microfabrication of transistor elements is approaching its limit. For these reasons, a new technology for elevating integration density further and raising functionality and memory capacity are now being sought. A stacked semiconductor device, or so-called three-dimensional semiconductor device, obtained by stacking a plurality of semiconductor chips is available as one such technology.
For instance, an arrangement in which a memory circuit is mounted on a parent chip that includes a CPU is described in Patent Document 1 as an example of implementation of a large-scale integrated circuit device without a change in chip area.
Further, a multilayer memory structure in which memory capacity is enlarged by adopting multiple layers of a memory cell array is described in Patent Document 2 as another example of implementation of a large-scale integrated circuit device without a change in chip area.
In a case where a plurality of semiconductor chips are stacked, inter-chip wiring for connecting the semiconductor chips to one another is required in addition to the wiring in the semiconductor chip surface. Although wire bonding usually is employed in inter-chip wiring, wire bonding is for interconnecting pads arranged on the semiconductor chip surface. In order to assure pad area (e.g., 100 μm square), therefore, a problem which arises is that a limitation is imposed upon the number of wires. Further, in a case where a plurality of semiconductor chips are stacked, pads are provided near the periphery of respective ones of the semiconductor chips in order to interconnect the semiconductor chips. Consequently, a problem which arises is that semiconductor chips of the same shape cannot be stacked. In particular, even if, when the number of usable wires is limited, it is attempted to provide a greater number of functions or enlarge memory capacity by stacking a plurality of semiconductor chips, the amount of data and number of signals transmitted between semiconductor chips increase to the extent of the increase in multiple functions and memory capacity. This is a factor that limits an improvement in performance.
Broadly speaking, there are two signal transmission techniques being considered as methods of solving these problems.
The first technique interconnects stacked semiconductor chips using through-wiring that passes through the semiconductor chips. For instance, Non-Patent Document 1 describes an example in which through-wiring for inter-chip wiring is formed by thinning a semiconductor substrate to 50 μm, providing a 10-μm-square hole and filling the hole with metal. Chip-to-chip wires can be laid out two-dimensionally in the chip surface by using this through-wiring, and several hundred chip-to-chip wires are possible. Furthermore, since the inter-chip wiring passes through the semiconductor chips, it is also possible to stack semiconductor chips of the same shape.
The second technique uses a non-contact interface in the transmission of data among a plurality of semiconductor chips. Broadly speaking, non-contact interfaces are of the capacitance-coupled type relying upon capacitance and inductance-coupled type using inductance. For instance, Non-Patent Document 2 describes a method and circuit in which pads are arranged on a semiconductor chip at intervals of 40 μm, two semiconductor chips are stacked with their surfaces face to face to thereby capacitively couple the pads, and data is transmitted using the capacitively coupled portions. Further, Non-Patent Document 3 describes a method and circuit in which coils each comprising a spiral inductor are arranged at intervals of 100 μm in a wiring area on a semiconductor chip, a plurality of the semiconductor chips are stacked with their surfaces in the same direction to thereby inductively couple the coils, and data is transmitted using the inductively coupled portions.
If signal transmission among a plurality of semiconductor chips is made possible using such through-wiring and capacitive or inductive coupling, the number of signals capable of being transmitted among semiconductor chips can be increased in comparison with an arrangement in which semiconductor chips are interconnected using wire bonding, and it becomes possible to stack not only memory chips but also semiconductor chips on which logic circuits or analog circuits, etc., have been formed. As a result, a semiconductor integrated circuit device can be provided with more functions and a larger memory capacity while the stacking of a plurality of semiconductor chips is made possible.
However, the technique for transmitting signals among stacked semiconductor chips using through-wiring requires a step of forming a hole referred to as a “through-via” that connects the top and bottom of the semiconductor substrate in order to perform signal transmission and filling the through-via with an electrically conductive material such as metal to thereby form wiring, and a step of encapsulation in an insulating material in order to insulate the through-wiring and semiconductor substrate. A problem which arises is that the process for manufacturing the semiconductor integrated circuit device is complicated, thereby raising manufacturing cost and prolonging manufacturing time.
Further, the technique for transmitting signals among stacked semiconductor chips using capacitive coupling is such that pads formed on the surfaces of the semiconductor chips must be arranged so as to face each other. This means that the number of layers of stacked semiconductor chips is limited to two, and it is difficult to stack the chips in three or more layers. A problem which arises is that a limitation is imposed upon an increase in number of functions and enlargement of memory capacity.
By contrast, the technique for transmitting signals among stacked semiconductor chips using inductive coupling, unlike capacitive coupling, is such that even if a semiconductor substrate exists between inductively coupled coils, the magnetic fields produced by the coils punch through the semiconductor substrate and, hence, it is possible to stack semiconductor chips in three or more layers. Accordingly, the functionality and memory capacity of a semiconductor integrated circuit device are increased while the stacking of semiconductor chips in three or more layers is made possible. Hence a signal transmission system using inductive coupling in inter-chip wiring is promising.
A signal transmission system that uses such inductive coupling will be described in detail with reference to FIGS. 11 to 13.
It is required in a signal transmission system using inductive coupling to provide a transmitting circuit on a data-transmit side including a transmitting coil and a driver for supplying a current corresponding to transmit data through the transmitting coil, and a receiving circuit on a data-receive side including a receiving coil, which is inductively coupled to the transmitting coil, and a circuit for reproducing data from the output current of the receiving coil.
FIG. 11 is a circuit diagram illustrating the configuration of a transmitting circuit used by a conventional signal transmission system, and FIG. 12 is a circuit diagram illustrating the configuration of a receiving circuit used by a conventional signal transmission system. Further, FIG. 13 is a timing chart illustrating the manner in which data is transmitted using the transmitting circuit shown in FIG. 11 and the receiving circuit shown in FIG. 12.
As illustrated in FIG. 11, the conventional transmitting circuit has a transmitting coil 100, a first driver circuit 101 and a second driver circuit 102 for supplying current through the transmitting coil 100 in a direction that corresponds to a change in transmit data, and a delay element 103 for delaying the transmit data supplied to the second driver circuit 102.
As illustrated in FIG. 12, the conventional receiving circuit has a receiving coil 300, a first resistor 301 and a second resistor 302 for converting current that flows into the receiving coil 300 to a voltage, and a receive-data reproducing circuit 303 for capturing a voltage, which is induced in the receiving coil 302 in response to the flow of current into the transmitting coil 100, at every rising or falling edge of a receive clock, reproducing the transmitted data (receive data) and outputting the reproduced data.
With inductive coupling it is well known that when the direction of current that flows into one coil changes, an induced current flows into the other coil coupled thereto. Consequently, if current is passed through the transmitting coil 100 when there is no change in the transmit data, power is consumed wastefully. Accordingly, the conventional transmitting circuit shown in FIG. 11 is such that only at the timing at which there is a change in the transmit data is current passed through the transmitting coil 100 in the direction corresponding to this change, as illustrated in FIG. 13. For example, a current is passed through the transmitting coil 100 in the negative direction in a case where transmit data changes from “1” to “0” and a current is passed through the transmitting coil 100 in the positive direction in a case where transmit data changes from “0” to “1”. The delay element 103 delays the transmit data supplied to either the first driver circuit 101 or second driver circuit 102 (the second driver circuit 102 in FIG. 11), thereby deciding the time (pulse width) over which current is passed through the transmitting coil 100.
When current is passed through the transmitting coil 100, an induced current flows into the receiving coil 300 and a voltage (referred to as an “induced voltage” below) is produced across the first resistor 301 and second resistor 302. The receive-data reproducing circuit 303 has, e.g., a switch circuit turned on and off by the receive clock, and a latch circuit that latches the output voltage of the switch circuit. The induced voltage produced across the first resistor 301 and second resistor 302 is captured using the switch circuit at every rising edge (or falling edge) of the receive clock, and the transmitted data (receive data) is reproduced based upon the polarity (“1” or “0”) of the induced voltage.